A group III nitride semiconductor has a direct transition type band gap of energy that corresponds to a region ranging from the visible light to ultraviolet light, and also exhibits excellent light emission efficiency. For this reason, it is manufactured as a semiconductor light emitting device such as a light emitting diode (LED) and a laser diode (LD) and used in various applications. In addition, the group III nitride semiconductor also has a potential of achieving excellent characteristics when used in electronic devices, as compared to the case where a conventional group III-V compound semiconductor is used.
Conventionally, a single crystal wafer of the group III nitride semiconductor has not been commercially available, and as a method for obtaining group III nitride semiconductors, a commonly used method grows crystals thereof on a single crystal wafer made of different materials. There is a great lattice mismatch between such a substrate made of different materials and the crystals of the group III nitride semiconductor epitaxially grown thereon. For example, when gallium nitride (GaN) is grown on a sapphire (Al2O3) substrate, there is a lattice mismatch of 16% between the two. When gallium nitride is grown on an SiC substrate, there is a lattice mismatch of 6%. In general, when there is a great lattice mismatch as in the above case, it will be difficult to directly grow crystals epitaxially on a substrate, and even when the crystals are grown, crystals with a favorable level of crystallinity cannot be attained, which is a problem.
Accordingly, when epitaxially growing the crystals of the group III nitride semiconductor on a sapphire single crystal substrate or an SiC single crystal substrate by a metal organic chemical vapor deposition (MOCVD) method, a method has been proposed and has been commonly conducted, in which a layer called a low temperature buffer layer composed of aluminum nitride (AlN) or aluminum gallium nitride (AlGaN) is first laminated on the substrate, and the crystals of the group III nitride semiconductor having a high temperature are epitaxially grown thereon (for example, refer to Patent Documents 1 and 2).
However, in the method described in Patent Documents 1 and 2, since there is basically no lattice matching between the substrate and the crystals of the group III nitride semiconductor grown thereon, a dislocation known as threading dislocation which extends towards the surface is included inside the grown crystals. For this reason, distortions of crystals occur, as a result of which sufficient intensity of light emission cannot be achieved without the optimization of crystal structure, and the problems such as the decline in the productivity also arise.
In addition, regarding the method in which an intermediate layer (buffer layer) composed of AlN or the like is formed on top of a substrate using a method other than an MOCVD method, followed by the formation of a layer thereon by an MOCVD method, for example, a method has been proposed in which, on top of the intermediate layer formed by a high-frequency sputtering process, a crystal having the same composition is grown by an MOCVD method (for example, refer to Patent Document 3). However, with the method disclosed in Patent Document 3, there is a problem in that crystals cannot be laminated reliably on a substrate in a favorable manner.
Accordingly, in order to reliably obtain satisfactory crystals, a method in which an intermediate layer was grown, followed by the annealing thereof in a mixed gas composed of ammonia and hydrogen (for example, refer to Patent Document 4), a method in which a buffer layer is formed at a temperature of 400° C. or higher by a DC sputtering process (for example, refer to Patent Document 5), or the like has been proposed. In addition, in Patent Documents 4 and 5, as a material used for a substrate, sapphire, silicon, silicon carbide, zinc oxide, gallium phosphide, gallium arsenide, magnesium oxide, manganese oxide, single crystals of a group III nitride based compound semiconductor, or the like, has been mentioned, and it has been disclosed that a sapphire a-plane substrate is particularly suitable among them.
On the other hand, a method is disclosed in which a reverse sputtering process using Ar gas is conducted as a pretreatment for a semiconductor layer when forming an electrode on the semiconductor layer (for example, refer to Patent Document 6). According to the method disclosed in Patent Document 6, by conducting a reverse sputtering process on the surface of a group III nitride compound semiconductor layer, characteristics in terms of electrical contact between the semiconductor layer and the electrode can be improved.
However, because all these methods described above are methods in which an intermediate layer is laminated on a substrate without being modified and a group III nitride compound semiconductor is then epitaxially grown thereon, there is a lattice mismatch between the substrate and the crystals of the group III nitride semiconductor, and thus satisfactory crystals cannot be obtained reliably, which has been a problem.    [Patent Document 1] Japanese Patent Publication No. 3026087    [Patent Document 2] Japanese Unexamined Patent Application, First Publication No. Hei 4-297023    [Patent Document 3] Japanese Examined Patent Application, Second Publication No. Hei 5-86646    [Patent Document 4] Japanese Patent Publication No. 3440873    [Patent Document 5] Japanese Patent Publication No. 3700492    [Patent Document 6] Japanese Unexamined Patent Application, First Publication No. Hei 8-264478